Offer Description
Who we are ?
Télécom Paris, part of the IMT (Institut Mines-Télécom) and a founding member of the Institut Polytechnique de Paris, is one of France’s top 5 general engineering schools.
The mainspring of Télécom Paris is to train, imagine and undertake to design digital models, technologies and solutions for a society and economy that respect people and their environment.
We are looking for a post-doctoral fellow to join our computer science and networks department. We are looking for someone with a passion in the field of timing anomalies in multi-core real-time systems.
This position is part of the CAOTIC collaborative project. It is funded by the French National Research Agency. CAOTIC brings together a number of French research groups working in the area of timing analysis and verification of critical embedded systems. The aim of the project is to develop new techniques for the verification of real-time constraints in multi-core and heterogeneous embedded architectures. Timing analysis of multi-core platforms is more difficult than that of single core platforms due to the presence of timing interference. Timing interference occurs when two activities conflict to access a shared hardware resource (cache, interconnect, memory banks, etc.) resulting in the delay of one of the activities. To verify the timing behaviour of a program on a multi-core architecture, it is necessary to exhaustively identify the interference channels present at the hardware/architecture level. It is then necessary to determine the effect of the interference passing through these channels on the timing behaviour of the program of interest. In some systems, this problem is made more difficult by the possible presence of timing anomalies: either counter-intuitive behaviour (a local acceleration leads to a global slowdown), or amplification (a local slowdown leads to a much larger global slowdown). The context of this position is the timing verification of programs in the presence of timing interference and timing anomalies.
Scope of the work: The person recruited will work on two topics. First, the work will focus on the study of the memory hierarchy of heterogeneous multi-core embedded architectures. The aim of this study will be to identify the channels, explicit or implicit, through which a system activity can interfere with the execution of a program on one of the cores, typically by delaying a memory access. A memory hierarchy representative of the target systems includes parallelism and non-preemptive activities, two elements that are known to lead to the appearance of timing anomalies. Thus, the study will also investigate the existence of timing anomalies in the memory hierarchy. Finally, the two phenomena, interference and timing anomalies, will have to be characterised. Ideally, an operational procedure for detecting their occurrence will be formalised and applied to realistic system models. Second, the work also cover the development of analysis techniques to compute safe upper bounds on the maximum duration of an execution trace in the presence of interference, when the micro-architecture is likely to produce timing anomalies. The presence of timing anomalies invalidates approaches based on adding a constant interference cost equal to the induced delay. It is then necessary to consider a set of scenarios that are sufficiently complete to ensure that the worst case is included. The work will involve identifying this set of scenarios and proposing a symbolic enumeration technique that can be scaled up to compute upper bounds.
Day-to-day responsibilities
– To carry out research missions in the field of timing anomalies in multi-core real-time systems
– To supervise and tutoring, e.g., of student projects
– To contribute to the reputation of the School, the Institut Mines-Télécom and the Institut Polytechnique de Paris
To be successful in this role, you must have a thorough theoretical and practical knowledge in the analysis of timing properties of multi-core real-time systems (WCET, cache analysis, schedulability tests, …)
You will need to be fluent in English and have a PhD or equivalent.
If you have a background in formal methods in particular model checking, come and join us!
Why join us?
You’ll be working in a fast-growing, pleasant, green and accessible environment (especially for people with disabilities) just 20 km from Paris (RER B and C suburban train lines, close to major roads, shared shuttle departing from Porte d’Orléans). You will benefit from :
Other information :
Application deadline: april 10, 2024
Job type : 12 months fixed-term contract
We recruit on the basis of skills, regardless of origin, age or gender, and all our positions are open to people with disabilities.
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STATUS: EXPIRED
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